1. Technical Field
The present invention relates to a jitter injection circuit, a pattern generator, a test apparatus, and an electronic device. More particularly, the present invention relates to a jitter injection circuit that generates a jittery signal containing jitter, a pattern generator that generates a data signal containing jitter, a test apparatus that tests a device under test using a test signal into which jitter is injected, and an electronic device provided with a self diagnostic section that tests a circuit under test using a test signal into which jitter is injected.
2. Related Art
A jitter tolerance testing is a type of testing performed for high speed communication devices and high speed serial I/O devices. For example, according to a recommendation from the ITU-T, a testing is defined in which jitter tolerance testing is performed by injecting jitter having a frequency of several hundred MHz into the communication data.
As a method for injecting jitter into a high frequency signal, a method is considered in which jitter is injected into a clock signal generated by a voltage controlled oscillator by injecting a modulated signal into a control input of the voltage controlled oscillator, and a data signal is then generated using the clock signal.
Another method is considered in which a variable delay circuit is disposed at a stage after a generator that generates a clock signal or a data signal and the jitter is injected by changing the delay control input of the variable delay circuit. An example of a jitter injection method using the variable delay circuit is disclosed in Pamphlet No. WO2007/049365.
During actual implementation of the electronic device, it is important to minimize the bit error ratio caused by the high frequency jitter component. Therefore, it is also desirable that the high frequency jitter be injected into the test apparatus testing the electronic device.
In a case where the jitter is generated by modulating the control input of the voltage controlled oscillator as described above, however, it is difficult to quickly modulate the clock signal with the control input, so that a frequency boundary of the generated jitter is only tens of MHz. In a case where the jitter is generated by changing the delay amount of the variable delay circuit, jitter having high frequency and large amplitude cannot be generated because the variable delay circuit requires time to catch up to the change of the delay setting section.